1. Field of the Invention
The invention relates to the field of MOS buffers, particularly those which receive TTL level signals and convert them to MOS level signals.
2. Prior Art
It is frequently necessary to convert binary signals which operate between first levels, to binary signals which operate between second levels. For example, signals compatible with emitter-coupled-logic are frequently converted to signal compatible with transistor-transistor logic (TTL). The present invention is particularly useful for converting TTL signals to signals compatible with metal-oxide-semiconductor (MOS) integrated circuits.
There are many circuits known in the prior art for converting TTL level signals to MOS level signals. Perhaps the closest prior art circuit for such conversion consists of an inverter, more specifically, a depletion mode transistor used as a load device coupled in series with an enhancement mode transistor. The TTL level signals are coupled to the gate of the enhancement mode transistor; the common junction between the two transistors provides an output signal.
For satisfactory operation of such an inverter, the transistors must be relatively large. For example, with current n-channel MOS technology, the length-to-width ratio of the input transistors are in the range of 150/5 to 250/5. If shorter channels are used, the lower level of the TTL signal may cause substantial conduction in the inverter and thus degrade the performance of the inverter. Even using these larger devices, the inverter's performance is not always satisfactory.
Other MOS buffers for converting TTL signals to MOS level signals are described in U.S. Pat. No. 4,048,518.